NSTL国家科技图书文献中心

1. Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache NSTL国家科技图书文献中心

Davy Million | Noelia Oliete-Escuín ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～2 - 共2页

摘要：The lack of concurrency and pipelining in the | memory sub-system of recent open-source RISC-V | processors, such as the CVA6 11https://github.com | /openhwgroup/cva6, is increasingly becoming the performance | bottleneck. Recent updates to the new RISC-V High

关键词： Concurrent computing | Program processors | Benchmark testing | Pipeline processing

2. Late Breaking Results: Iterative Design Automation for Train Control with Hybrid Train Detection NSTL国家科技图书文献中心

Stefan Engels | Robert Wille - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～2 - 共2页

摘要：To increase the capacity of existing railway | infras-tructure, the European Train Control System | (ETCS) allows the introduction of virtual subsections | . As of today, the planning of such systems is mainly | done by hand. Previous design automation methods

关键词： Design automation | Runtime | Layout | Europe | Aerospace electronics | Control systems | Rail transportation

3. Alleviating Barren Plateaus in Parameterized Quantum Machine Learning Circuits: Investigating Advanced Parameter Initialization Strategies NSTL国家科技图书文献中心

Muhammad Kashif | Muhammad Rashid ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：Parameterized quantum circuits (PQCs) have | emerged as a foundational element in the development and | applications of quantum algorithms. However, when initialized | with random parameter values, PQCs often exhibit | barren plateaus (BP). These plateaus, characterized by

关键词： Training | Quantum algorithm | Neural networks | Qubit | Machine learning | Quantum circuit | Optimization

4. Multi-Agent Reinforcement Learning for Thermally-Restricted Performance Optimization on Manycores NSTL国家科技图书文献中心

Heba Khdr | Mustafa Enes Batur ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：The problem of performance maximization under | a thermal constraint has been tackled by means of | dynamic voltage and frequency scaling (DVFS) in many | system-level optimization techniques. State-of-the-art | ones have exploited Su-pervised Learning (SL) to

关键词： Adaptation models | Temperature distribution | Runtime | Q-learning | System performance | Training data | Voltage

5. Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks NSTL国家科技图书文献中心

Paul R. Genssler | Sandy A. Wasif ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：Hyperdimensional Computing (HDC) is an | emerging paradigm that stands as a compelling alternative | to conventional Deep Learning algorithms. HDC holds | four key promises. First, the ability to learn from | little data. Second, to be robust against noise in this

关键词： Deep learning | Computational modeling | Neural networks | Noise | Hardware | Encoding | Computational efficiency

6. MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications NSTL国家科技图书文献中心

Tousif Rahman | Gang Mao ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：System-on-Chip Field-Programmable Gate Arrays | (SoC-FPGAs) offer significant throughput gains for | machine learning (ML) edge inference applications via | the design of co-processor accelerator systems | . However, the design effort for training and translating

关键词： Training | Power demand | Scalability | Pipelines | Throughput | Inference algorithms | System-on-chip

7. LoADM: Load-Aware Directory Migration Policy in Distributed File Systems NSTL国家科技图书文献中心

Yuanzhang Wang | Peng Zhang ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：Distributed file systems often suffer from | load imbalance when encountering skewed workloads. A | few directories can become hotspots due to frequent | access. Failure to migrate these high-load directories | promptly will result in node overload, which can

关键词： Analytical models | File systems | Peer-to-peer computing | Proposals | Particle swarm optimization | Load modeling

8. Securing ISW Masking Scheme Against Glitches NSTL国家科技图书文献中心

Sofiane Takarabt | Javad Bahrami ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～2 - 共2页

摘要：Ishai-Sahai-Wagner (ISW) masking scheme has | been proposed in literature to protect cryptographic | circuitries against side-channel analysis attacks. Although | provably secure from a theoretical standpoint, its | hardware implementation may not be secure as such

关键词： Logic gates | Maintenance engineering | Hardware | Delays | Cryptography

9. VeriBug: An Attention-Based Framework for Bug Localization in Hardware Designs NSTL国家科技图书文献中心

Giuseppe Stracquadan... | Sourav Medya ... - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～2 - 共2页

摘要：In recent years, there has been an exponential | growth in the size and complexity of System-on-Chip | (SoC) designs targeting different specialized | applications. The cost of an undetected bug in these systems | is much higher than in traditional processors, as

关键词： Location awareness | Deep learning | Program processors | Costs | Computer bugs | Debugging | Hardware

10. Automated Traffic Scenario Description Extraction Using Video Transformers NSTL国家科技图书文献中心

Aron Harder | Madhur Behl - 《2024 Design, Automation & Test in Europe Conference & Exhibition: DATE 2024, Valencia, Spain, 25-27 March 2024, [v.1]》 - Design, Automation & Test in Europe Conference & Exhibition - 2024, - 1～6 - 共6页

摘要：Scenario Description Languages (SDLs) serve as | high-level encodings, offering an interpretable | representation of traffic situations encountered by autonomous | vehicles (AVs). Their utility extends to critical safety | analyses, such as identifying analogous traffic scenarios

摘要：The lack of concurrency and pipelining in the | memory sub-system of recent open-source RISC-V | processors, such as the CVA6 11https://github.com | /openhwgroup/cva6, is increasingly becoming the performance | bottleneck. Recent updates to the new RISC-V High

关键词： Concurrent computing | Program processors | Benchmark testing | Pipeline processing

摘要：To increase the capacity of existing railway | infras-tructure, the European Train Control System | (ETCS) allows the introduction of virtual subsections | . As of today, the planning of such systems is mainly | done by hand. Previous design automation methods

关键词： Design automation | Runtime | Layout | Europe | Aerospace electronics | Control systems | Rail transportation

摘要：Parameterized quantum circuits (PQCs) have | emerged as a foundational element in the development and | applications of quantum algorithms. However, when initialized | with random parameter values, PQCs often exhibit | barren plateaus (BP). These plateaus, characterized by

关键词： Training | Quantum algorithm | Neural networks | Qubit | Machine learning | Quantum circuit | Optimization

摘要：The problem of performance maximization under | a thermal constraint has been tackled by means of | dynamic voltage and frequency scaling (DVFS) in many | system-level optimization techniques. State-of-the-art | ones have exploited Su-pervised Learning (SL) to

关键词： Adaptation models | Temperature distribution | Runtime | Q-learning | System performance | Training data | Voltage

摘要：Hyperdimensional Computing (HDC) is an | emerging paradigm that stands as a compelling alternative | to conventional Deep Learning algorithms. HDC holds | four key promises. First, the ability to learn from | little data. Second, to be robust against noise in this

关键词： Deep learning | Computational modeling | Neural networks | Noise | Hardware | Encoding | Computational efficiency

摘要：System-on-Chip Field-Programmable Gate Arrays | (SoC-FPGAs) offer significant throughput gains for | machine learning (ML) edge inference applications via | the design of co-processor accelerator systems | . However, the design effort for training and translating

关键词： Training | Power demand | Scalability | Pipelines | Throughput | Inference algorithms | System-on-chip

摘要：Distributed file systems often suffer from | load imbalance when encountering skewed workloads. A | few directories can become hotspots due to frequent | access. Failure to migrate these high-load directories | promptly will result in node overload, which can

关键词： Analytical models | File systems | Peer-to-peer computing | Proposals | Particle swarm optimization | Load modeling

摘要：Ishai-Sahai-Wagner (ISW) masking scheme has | been proposed in literature to protect cryptographic | circuitries against side-channel analysis attacks. Although | provably secure from a theoretical standpoint, its | hardware implementation may not be secure as such

关键词： Logic gates | Maintenance engineering | Hardware | Delays | Cryptography

摘要：In recent years, there has been an exponential | growth in the size and complexity of System-on-Chip | (SoC) designs targeting different specialized | applications. The cost of an undetected bug in these systems | is much higher than in traditional processors, as

关键词： Location awareness | Deep learning | Program processors | Costs | Computer bugs | Debugging | Hardware

摘要：Scenario Description Languages (SDLs) serve as | high-level encodings, offering an interpretable | representation of traffic situations encountered by autonomous | vehicles (AVs). Their utility extends to critical safety | analyses, such as identifying analogous traffic scenarios

关键词： Training | Solid modeling | Three-dimensional displays | Convolution | Predictive models | Transformers | Encoding

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